module stt(
  // Clock Input (50 MHz)
  input  CLOCK_50,
  input  CLOCK_27,

  //  Push Buttons
  input  [3:0]  KEY,
  //  DPDT Switches 
  input  [17:0]  SW,
  //  7-SEG Displays
  output  [6:0]  HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7,
  //  LEDs
  output  [8:0]  LEDG,  //  LED Green[8:0]
  output  [17:0]  LEDR,  //  LED Red[17:0]
//	LCD Module 16X2
   inout  [7:0]	LCD_DATA,	//	LCD Data bus 8 bits
   output		LCD_ON,		//	LCD Power ON/OFF
   output		LCD_BLON,	//	LCD Back Light ON/OFF
   output		LCD_RW,		//	LCD Read/Write Select, 0 = Write, 1 = Read
   output		LCD_EN,		//	LCD Enable
   output		LCD_RS,		//	LCD Command/Data Select, 0 = Command, 1 = Data

//		SDRAM Interface
   inout  [15:0] DRAM_DQ,	//	SDRAM Data bus 16 Bits
   output [11:0] DRAM_ADDR,	//	SDRAM Address bus 12 Bits
   output		DRAM_LDQM,	//	SDRAM Low-byte Data Mask 
   output		DRAM_UDQM,	//	SDRAM High-byte Data Mask
   output		DRAM_WE_N,	//	SDRAM Write Enable
   output		DRAM_CAS_N,	//	SDRAM Column Address Strobe
   output		DRAM_RAS_N,	//	SDRAM Row Address Strobe
   output		DRAM_CS_N,	//	SDRAM Chip Select
   output		DRAM_BA_0,	//	SDRAM Bank Address 0
   output		DRAM_BA_1,	//	SDRAM Bank Address 0
   output		DRAM_CLK,	//	SDRAM Clock
   output		DRAM_CKE,	//	SDRAM Clock Enable

  //  GPIO Connections
  inout  [35:0]  GPIO_0, GPIO_1,
  
  
  //AUDIO CODEC
  	input wire AUD_ADCDAT,
	inout wire AUD_BCLK,
	inout wire AUD_ADCLRCK,
	inout wire AUD_DACLRCK,
	output wire AUD_DACDAT,
	output wire AUD_XCK,
	
	output wire I2C_SCLK,
	inout wire I2C_SDAT



);

//  set all inout ports to tri-state
assign	DRAM_DQ		=	16'hzzzz;
assign  GPIO_0    =  36'hzzzzzzzzz;
assign  GPIO_1    =  36'hzzzzzzzzz;

wire RST;
assign RST = KEY[0];

// Connect dip switches to red LEDS
assign LEDR[17:0] = SW[17:0];

//	LCD ON
assign	LCD_ON		=	1'b1;
assign	LCD_BLON	=	1'b1;




wire clk_0;
sram_pll sram_pll_inst(
	.inclk0(CLOCK_50),
	.c0(DRAM_CLK),
	.c1(clk_0)
);
aud_pll aud_pll_inst(
	.inclk0(CLOCK_27),
	.c0(AUD_XCK)
);


sopc_system our_cpu(
// 1) global signals:
    .clk_0(clk_0),
    .reset_n(RST),


	// the_audio_0
	.AUD_ADCDAT_to_the_audio_0(AUD_ADCDAT),
	.AUD_ADCLRCK_to_and_from_the_audio_0(AUD_ADCLRCK),
	.AUD_BCLK_to_and_from_the_audio_0(AUD_BCLK),
	.AUD_DACDAT_from_the_audio_0(AUD_DACDAT),
	.AUD_DACLRCK_to_and_from_the_audio_0(AUD_DACLRCK),
				
				
	.I2C_SCLK_from_the_audio_and_video_config_0(I2C_SCLK),
	.I2C_SDAT_to_and_from_the_audio_and_video_config_0(I2C_SDAT),

 // the_sdram
   .zs_addr_from_the_sdram(DRAM_ADDR),
   .zs_ba_from_the_sdram({DRAM_BA_1,DRAM_BA_0}),
   .zs_cas_n_from_the_sdram(DRAM_CAS_N),
   .zs_cke_from_the_sdram(DRAM_CKE),
   .zs_cs_n_from_the_sdram(DRAM_CS_N),
   .zs_dq_to_and_from_the_sdram(DRAM_DQ),
   .zs_dqm_from_the_sdram({DRAM_UDQM,DRAM_LDQM}),
   .zs_ras_n_from_the_sdram(DRAM_RAS_N),
   .zs_we_n_from_the_sdram(DRAM_WE_N)

  );


//  output  [ 31: 0] out_port_from_the_pio_0;
//  input   [ 31: 0] in_port_to_the_pio_0;
endmodule
